Referring to FIGS. 1A and 1B, a typical CMOS open drain bus driver 10 includes a pulse source 12 and a pre-driver stage 14 comprising a PMOS device 14a and an NMOS device 14b, with the PMOS device 14a having a tie point (labeled "VD") coupled to a power supply VDD. As shown in FIG. 1B, the power supplies VDD and VTT provide voltages of VD and VT, respectively. In addition, the driver 10 includes a driver stage 16 comprising a plurality (twelve (12) in this example) of NMOS devices 16 coupled in parallel to one another and having open drains, as indicated by the open tie points labelled "DR." These drains are shown in FIG. 1A as being connected to a slot S3 but, of course, the driver 10 could be connected to any of the slots S1-S5.
Referring to FIG. 1C, a bus 20 comprises a plurality of slots S1-S5 each of which may be coupled to a receiver. In FIG. 1C, the receivers are represented by capacitors 22a-22e, respectively. The bus driver 10 of FIG. 1A is shown as being connected to slot S3. In addition, the bus 20 includes transmission line segments TB having inputs and outputs which are referenced to a ground plane 24. It is well known in the art that such transmission line segments can be embodied as conductive lines printed on a substrate. The bus 20 also includes parallel stubs, which are transmission line segments TC having respective inputs and outputs connected to a ground plane. The transmission line segments TB and TC are represented generally by reference numeral 28. The two ends of the bus 20 are terminated with 50.OMEGA. resistors, which are in turn tied to power supply terminating voltage VT at tie points 26a and 26b, respectively.
State of the art CMOS open drain bus drivers of the type depicted in FIG. 1A produce excessive ringing due to the large di/dt (i.e., large rate of change of current with respect to time) that occurs when the twelve (12) N45P0 NMOS devices 16 are turned off. This excessive ringing is shown in FIGS. 2 and 3, which depict the voltage waveforms at slots S1-S5 of the bus 20 of FIG. 1C. FIG. 2 shows the waveforms when the driver 10 (FIG. 1A) is coupled to slot S1, and FIG. 3 depicts the waveforms when the driver is coupled to slot S3. This di/dt, which is typically in the range of 150 mA/nS, and the inductance L associated with the transmission line network cause a gross overshoot of the line terminating voltage, VTT=1.5 V, due to the inductive voltage L di/dt. The initial edge of the overshoot is subsequently propagated down the bus while undergoing reflections, thus producing excessive ringing at the receivers coupled to slots S1-S5.
The waveforms depicted in FIGS. 2 and 3 were generated by a computer simulation using a model of the driver 10 and bus 20. In the model, the receivers or capacitances 22a-22e were represented by 8 pF capacitors. The characteristic impedance of the transmission line segments 28 was set to 50.OMEGA.. The power supplies VDD and VTT were set to 3.3 V and 1.5 V, respectively. The length of the transmission lines TB and TC were represented as time delays of 0.2 nS and 0.4 nS, respectively. The waveforms of FIGS. 2 and 3 demonstrate the severe voltage overshoot (above the 1.5 V terminating voltage) and ringing that occur when the driver 10 is turned off. A primary goal of the present invention is to provide a bus driver having means for reducing the severity of the ringing exhibited by these waveforms.
U.S. Pat. No. 5,179,299, Jan. 12, 1993, titled "CMOS Low Output Voltage Bus Driver," discloses a digital computer data transfer system including a bus driver that purportedly reduces data bus voltage swings between logic HIGH and logic LOW levels by defining minimum and maximum bus voltages which lie between the logic HIGH and LOW levels, thus lowering bus transition times. Positive and negative overshoot of the reduced bus logic levels are prevented by "clamping diode" transistors. The system disclosed by this patent is believed to have the following disadvantages: (a) the chip in which it is implemented requires an additional supply voltage (VHO=1.0 V), which then requires additional package pins; (b) the driver dissipates power in both the High and Low states, and in both states NMOS 228 and 242 are ON; and (c) when the driver is disabled (DISABLE=5 V) and another driver on the bus is not disabled and driving a High, the NMOS 242 in the disabled driver will conduct; likewise, when driving a Low, the NMOS 228 in the disabled driver will conduct.